1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of metal gate electrodes used in semiconductor devices.
2. Description of the Related Art
As the size and scaling of semiconductor device technology is reduced, aspects of device design and fabrication that previously gave rise to only second-order effects in long-channel devices can no longer be ignored. For example, the reduced scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. As a result, CMOS technology is increasingly replacing silicon dioxide gate dielectrics and polysilicon gate conductors with high dielectric constant (high-k) dielectrics in combination with metal gate electrodes formed from a gate stack of polysilicon and one or more metal layers. With such technologies, the metal gate layers not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower sheet resistance.
While high-k dielectrics in conjunction with metal gate electrodes advantageously exhibit improved transistor performance, the use of new metal layer technologies can create new technical challenges. For example, conventional NMOS and PMOS metal gate technologies use metal materials that are not thermally stable with polysilicon. One of the primary issues arises when a poly/metal gate electrode is formed by capping a metal layer with a polycrystalline silicon, an example of which is illustrated in FIG. 1, which depicts a partial cross-sectional view of a semiconductor structure 1 including a substrate 2, a dielectric layer 6 and a conventionally etched gate electrode 3 constructed from a polysilicon layer 8 formed over a metal layer 4 (e.g., TaC). With such poly/metal gate structures, there can be a low-level diffusion of silicon from the polycrystalline 8, through the metal layer 4 and into the gate dielectric 6 after high temperature anneals (such as occur during a source/drain activation anneal). This diffusion appears to be the result of silicon diffusing through the metal grain boundaries and results in the formation of nodules 5, 7, 9. As the metal layer 4 is made thinner, the amount of silicon reaching the gate dielectric 6 increases, which increases the leakage current of the device. Though a thinner metal layer increases the interaction between the polysilicon and the HfO2 results in devices with high leakage current, it can be desirable to have a thinner metal layer to minimize the exposure to chemically and physically aggressive gate etch processes that can pit the underlying dielectric and damage the substrate. In addition, prior metal gate fabrication processes relied on overly complex processes that did not address the thermal stability or leakage current problems.
Accordingly, a need exists for an improved poly/metal gate electrode and manufacture method for minimizing the interaction between the polysilicon and the high-k dielectric and subsequently reducing leakage current. There is also a need for a controlled fabrication process that reliably produces thermally stable metal gate electrodes. In addition, there is a need for improved semiconductor device structure and manufacturing process to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.